Title :
Comments on "Test efficiency analysis of random self-test of sequential circuits"
Author :
Pilarski, Slawomir
Author_Institution :
Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
Abstract :
For the original article see ibid., vol. 10, no. 3, p. 390-98 (1991). In the aforementioned paper by S. Sastry and A. Majumdar the testing effectiveness of random pattern techniques is studied and the authors claim to give complete analytical solutions to the problem of estimating such an effectiveness. The commenters point out that the analysis is based on an oversimplified circuit model, and, therefore, the conclusions are invalid. They comment on the analysis and explain its weakness, especially with respect to the built-in self-test (BIST) technique referred to as circular self-test path (CSTP).<>
Keywords :
automatic testing; built-in self test; integrated circuit testing; integrated logic circuits; logic testing; sequential circuits; BIST technique; built-in self-test; circuit model; circular self-test path; random pattern techniques; random self-test; sequential circuits; test efficiency analysis; Automatic testing; Built-in self-test; Circuit analysis computing; Circuit testing; Clocks; Pattern analysis; Sampling methods; Sequential analysis; Sequential circuits; State estimation;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
