BiCMOS technology with 60 GHz n-p-n bipolar and 0.25 mu m CMOS

Author

Warnock, James ; Shahidi, Ghavam G. ; Dasvari, B. ; Wu, Benjamin ; Taur, Yuan ; Wong, C. ; Jenkins, K. ; Chen, Chih-Liang

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown heights, NY, USA

Volume

13

Issue

11

fYear

1992

Firstpage

578

Lastpage

580

Abstract

A BiCMOS technology has been developed that integrates a high-performance self-aligned double-polysilicon bipolar device into an advanced 0.25 mu m CMOS process. The process sequence has been tailored to allow maximum flexibility in the bipolar device design without perturbation of the CMOS device parameters. Thus, n-p-n cutoff frequencies as high as 60 GHz were achieved while maintaining a CMOS ring oscillator delay per stage of about 54 ps at 2.5 V supply comparable to the performance in the CMOs-only technology. BiCMOS and BiNMOS circuits were also fabricated. BiNMOS circuits exhibited approximately=45% delay improvement compared to CMOS-only circuits under high load conditions at 2.5 V.<>

Keywords

BiCMOS integrated circuits; delays; integrated circuit technology; 0.25 micron; 54 ps; 60 GHz; BiCMOS technology; BiNMOS circuits; CMOS device parameters; CMOS ring oscillator delay; bipolar device design; delay improvement; high load conditions; n-p-n cutoff frequencies; self-aligned double-polysilicon bipolar device; BiCMOS integrated circuits; CMOS process; CMOS technology; Cutoff frequency; Delay; Dielectrics; Implants; Metallization; Passivation; Rapid thermal annealing;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.192841

Filename

192841