Low-power clock distribution using multiple voltages and reduced swings

Author

Pangjun, Jatuchai ; Sapatnekar, Sachin S.

Author_Institution

Dept. of Electr. & Comput. Eng., Minnesota Univ., USA

Volume

10

Issue

3

fYear

2002

fDate

6/1/2002 12:00:00 AM

Firstpage

309

Lastpage

318

Abstract

Clock networks account for a significant fraction of the power dissipation of a chip and are critical to performance. This paper presents theory and algorithms for building a low-power clock tree by distributing the clock signal at a lower voltage and translating it to a higher voltage at the utilization points. Two low-power schemes are used: reduced swing and multiple-supply voltages. We analyze the issue of tree construction and present conclusions relevant to various technology generations according to the NTRS. Our experimental results show that power savings of an average of 45% are possible for a 0.25 /spl mu/m technology using multiple supply voltages, and about 32% using a single external supply voltage.

Keywords

CMOS digital integrated circuits; SPICE; VLSI; clocks; integrated circuit design; integrated circuit interconnections; low-power electronics; trees (mathematics); 0.25 micron; NTRS; SPICE simulations; VLSI; clock networks; clock signal distribution; clock skew; high-performance interconnect; low-power clock distribution; low-power clock tree; multiple voltages; multiple-supply voltages; power dissipation; power savings; reduced swing CMOS buffer; reduced swings; single external supply voltage; static CMOS inverter; technology generations; tree construction; utilization points; Buildings; Capacitance; Clocks; Integrated circuit interconnections; Power dissipation; Power system interconnection; Very large scale integration; Voltage; Wire;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2002.1043334

Filename

1043334