Inverter Hardness Predictions and Correlation with LSI Device Failure Doses

Inverter test devices derived from lots of CMOS/SOS/LSI microprocessors, arithmetic logic units, and memories both hardened and unhardened types were irradiated with Cobalt 60 radiation together with LSI samples from the same lots. Failure doses for the LSI devices were compared to predicted failure doses based on the inverter data and a failure criterion that the threshold voltage, VTN must not penetrate the depletion region. The results showed that correlation of LSI device failure doses with predicted values was within factors of 1 to 10 for hardened and 2 for unhardened devices. The factor for hardened devices could be reduced to 3 by relaxing the criterion to allow a one volt penetration of the depletion region.