An ultra-fast instruction set simulator

Author

Zhu, Jianwen ; Gajski, Daniel D.

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

Volume

10

Issue

3

fYear

2002

fDate

6/1/2002 12:00:00 AM

Firstpage

363

Lastpage

373

Abstract

In this paper, we present new techniques which further improve the static compilation-based instruction set architecture (ISA) simulation by the aggressive utilization of the host machine resources. Such utilization is achieved by defining a low-level code-generation interface specialized for ISA simulation, rather than the traditional approaches which use C as a code-generation interface. We are able to perform the simulation at a speed of up to 10/sup 2/ millions of simulated instructions per second (MIPS) on a 270 MHz Ultra-5 workstation. This result is only on average 1.6 times slower than the native execution on the host machine, the fastest to the best of our knowledge.

Keywords

application program interfaces; embedded systems; hardware-software codesign; instruction sets; logic simulation; program compilers; reduced instruction set computing; virtual machines; API; RISC like virtual machine; embedded systems; hardware-software cosimulation; host machine resources; instruction set architecture simulation; internal state; logic simulation; low-level code-generation interface; processor registers; register allocator; retargetable compiler; static compilation-based simulation; system level; ultrafast instruction set simulator; virtual prototyping; Application software; Computational modeling; Computer aided instruction; Computer simulation; Hardware; Instruction sets; Logic; Process design; Registers; Workstations;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2002.1043339

Filename

1043339