Time Lag of Secondary ESD in Millimeter-Size Spark Gaps

This study relates to the delay of secondary electrostatic discharges (ESDs). The first motivation for this study is the fact that the delay value is a required input parameter for the simulation of the secondary ESD. The second motivation is that this delay is one limiting factor for the usage of spark gaps as protection devices. The objective is to determine the delay for different intended and unintended spark gap structures as this time delay will influence the peak current and rise time of the secondary ESD across these gaps. The intended application is ESD protection in consumer products, for that reason 0.5-3 mm gap distances and voltages up to 14 kV are considered at different humidity levels. Very long time lags are observed for clean sphere-to-sphere gaps requiring average field strengths >200 kV/cm to achieve a breakdown in a few nanoseconds in dry air. Humidity is shown to strongly reduce the time lag. However, if printed circuit board (PCB) spark gap geometries are considered the time lags are much smaller. Similar shorter lag times have been found in geometries that resemble more unintentional breakdown locations in a product.