Ultra-low power full adder circuit using SOI double-gate MOSFET devices

Proposed is a new, efficient design of a hybrid full adder cell combining two logic styles and a negative differential resistance device realised in a fully depleted silicon on insulator double-gate MOSFET technology. Simulation results show significant (70%) power savings for asymmetric gate work-function and independent gate control full adders with respect to standard CMOS circuits, with lower device count and comparable delay figures.