DC analysis of current mode logic

Author

Treadway, Ronald L.

Author_Institution

Adv. Micro Devices, Sunnyvale, CA, USA

Volume

5

Issue

2

fYear

1989

fDate

3/1/1989 12:00:00 AM

Firstpage

21

Lastpage

35

Abstract

A closed-form solution to finding the optimum signal swing for CML (current-mode logic) is illustrated, based on a few parameters of the minimum geometry transistor in a given technology. A simplified transistor model is used to develop the concept of noise margin optimized for both transistor and circuit parameters. It is shown that the voltage swing of the CML gate is not an arbitrary choice for the circuit designer but is deterministic. The effects of gate fan-in and series gating are then included as part of the closed-form solution, yielding an optimized set of parameters for defining all logic functions. Calculation of the maximum fan-out as well as bias regulators and calculation of the voltage drops in the power buses of chip layouts are treated. The procedure described has been used to develop a CML cell library for producing high-performance interface and networking circuits.<>

Keywords

emitter-coupled logic; integrated logic circuits; logic design; logic gates; CML cell library; DC analysis; ECL; bias regulators; chip layouts; circuit parameters; closed-form solution; current mode logic; gate fan-in; high-performance interface; logic gates; maximum fan-out; minimum geometry transistor; networking circuits; noise margin; optimum signal swing; power buses; series gating; transistor model; voltage drops; Circuit noise; Circuit synthesis; Closed-form solution; Geometry; Inverters; Large scale integration; Logic gates; Product design; Switches; Voltage;

fLanguage

English

Journal_Title

Circuits and Devices Magazine, IEEE

Publisher

ieee

ISSN

8755-3996

Type

jour

DOI

10.1109/101.19320

Filename

19320