DocumentCode
851715
Title
VLSI implementation of a tree searched vector quantizer
Author
Kolagotla, Ravi K. ; Yu, Shu-Sun ; JáJá, Joseph F.
Author_Institution
Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA
Volume
41
Issue
2
fYear
1993
fDate
2/1/1993 12:00:00 AM
Firstpage
901
Lastpage
905
Abstract
The VLSI design and implementation of a tree-searched vector quantizer is presented. The number of processors needed is equal to the depth of the tree. All processors are identical, and data flow between processors is regular. No global control signals are needed. The processors have been fabricated using 2 μm N -well process on a 7.9×9.2 mm die. Each processor chip contains 25000 transistors and has 84 pins. The processors have been thoroughly tested at a clock frequency of 20 MHz
Keywords
VLSI; data compression; digital signal processing chips; image coding; trees (mathematics); vector quantisation; 2 micron; 20 MHz; VLSI implementation; design; image compression; tree searched vector quantizer; Bit rate; Clocks; Discrete cosine transforms; Discrete transforms; Distortion measurement; Frequency; Image coding; Image storage; Pins; Signal processing algorithms; Testing; Vector quantization; Very large scale integration;
fLanguage
English
Journal_Title
Signal Processing, IEEE Transactions on
Publisher
ieee
ISSN
1053-587X
Type
jour
DOI
10.1109/78.193225
Filename
193225
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