Title :
Diagnosing arbitrary defects in logic designs using single location at a time (SLAT)
Author :
Huisman, Leendert M.
Author_Institution :
IBM Microelectron. Div., Essex Junction, VT, USA
Abstract :
A new form of logic diagnosis is described that is suitable for diagnosing fails in combinational logic. It can diagnose defects that can affect arbitrarily many elements in the integrated circuit. It operates by first identifying patterns during which only one element is affected by the defect, and then diagnosing the fails observed during the application of such patterns, one pattern at a time. Single stuck-at faults are used for this purpose, and the aggregate of stuck-at fault locations thus identified is then further analyzed to obtain the most accurate estimate of the identities of those elements that can be affected by the defect. This approach to logic diagnosis is as effective as that of classical stuck-at fault-based diagnosis, when the latter applies, but is far more general. In particular, it can diagnose fails caused by bridges and opens as well as fails caused by regular stuck-at faults.
Keywords :
failure analysis; integrated circuit testing; logic testing; IC test; SLAT; arbitrary defect diagnosis; bridge faults; combinational logic; logic fault diagnosis; open faults; single location at a time fault diagnosis; single stuck-at fault locations; Automatic testing; Circuit faults; Circuit testing; Fault diagnosis; Integrated circuit testing; Logic circuits; Logic design; Logic devices; Logic testing; Pins;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2003.816206
