Grouping variables into multiport memories for data path synthesis

Grouping registers into register files for efficiently implementing large VLSI chips, based on multiport memories, is being used in the design of many high-speed RISC and superscalar processors. An efficient design methodology for grouping variables into multiport memories, which is an essential step for multiport memory-based data path synthesis, is presented. The technique not only groups variables into a minimum number of multiport memory modules, but also simultaneously minimizes the number of registers in each memory module. The minimization problem has been formulated as a zero-one integer linear programming problem. Experiments on benchmarks show very promising results