Modulo 3 residue checker: new results on performance and cost

Author

Watterson, James W. ; Hallenbeck, Jill J.

Author_Institution

Center for Digital Syst. Res., Res. Triangle Inst., Research Triangle Park, NC, USA

Volume

37

Issue

5

fYear

1988

fDate

5/1/1988 12:00:00 AM

Firstpage

608

Lastpage

612

Abstract

The performance and cost of a modulo-3 residue code checker that has been attached to a pipelined serial multiplier to provide a concurrent self-test capability are considered. Analytical results are derived for error detection coverage and minimum error latency; these quantities are observed to be in agreement with simulation results obtained by using ISPS, a register-transfer language. The residue checker error detection coverage and minimum error latency are observed to be dependent on the statistical properties of the multiplier input operands. The checker and serial multiplier were implemented in 4-μm NMOS, using a standard cell design. The residue code checker required approximately half of the total silicon area

Keywords

automatic testing; digital arithmetic; error detection; field effect integrated circuits; integrated circuit testing; multiplying circuits; performance evaluation; pipeline processing; 4-μm NMOS; built in test; concurrent self-test; error detection coverage; minimum error latency; modulo-3 residue code checker; multiplier input operands; pipelined serial multiplier; standard cell design; Analytical models; Built-in self-test; Circuit testing; Costs; Delay; Digital systems; Integrated circuit reliability; MOS devices; Maintenance; Silicon;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.4612

Filename

4612