Implementation issues of 2-dimensional polynomial multipliers for signal processing using residue arithmetic

The residue number system (RNS) has been considered a useful tool for digital signal processing (DSP) since it can support parallel, carry-free, high-speed arithmetic. The polynomial residue number system (PRNS) enjoys all the RNS advantages and is capable of performing the useful DSP operation of polynomial multiplication in a totally parallel fashion and with minimum multiplication count provided that an appropriate modular arithmetic ring is chosen. However, the PRNS has one limitation: that is the size of the ring used for the arithmetic is proportional to the size of the polynomials to be multiplied. As a result, to multiply large polynomials in a fixed-size arithmetic ring, one must involve two-dimensional PRNS techniques. The authors describe these two-dimensional PRNS techniques and offer array implementations of two-dimensional PRNS polynomial multipliers. The proposed arrays are modular and pipelinable, and thus suitable for VLSI implementations.