• DocumentCode
    852927
  • Title

    Maze routing with buffer insertion and wiresizing

  • Author

    Lai, Minghorng ; Wong, D.F.

  • Author_Institution
    Cadence Design Syst. Inc., San Jose, CA, USA
  • Volume
    21
  • Issue
    10
  • fYear
    2002
  • fDate
    10/1/2002 12:00:00 AM
  • Firstpage
    1205
  • Lastpage
    1209
  • Abstract
    The authors propose an elegant formulation of the Maze Routing with Buffer Insertion and Wiresizing problem as a graph-theoretic shortest path problem. This formulation provides time and space performance improvements over previously proposed dynamic programming based techniques. Routing constraints such as wiring obstacles and restrictions on buffer locations and types are easily incorporated in the formulation. They construct a buffer planning (BP)-graph such that the length of every path in this graph is equal to the Elmore delay. Therefore, finding the minimum Elmore delay path becomes a finite shortest path problem. The buffer choices and insertion locations are represented as the vertices in the BP-graph. The interconnect wires are sized by constructing a look-up table for buffer-to-buffer wiresizing solutions. The authors also provide a technique that is able to tremendously improve the runtime. Experiments show improvements over previously proposed methods.
  • Keywords
    VLSI; circuit layout CAD; flow graphs; integrated circuit layout; network routing; table lookup; buffer insertion; buffer location restrictions; buffer planning graph; delay minimization; finite shortest path problem; graph-theoretic shortest path problem; interconnect wires; layout design; look-up table; maze routing; minimum Elmore delay path; routing constraints; very large scale integration design; wiresizing; wiring obstacles; Delay; Dynamic programming; Integrated circuit interconnections; Process design; Routing; Shortest path problem; Table lookup; Very large scale integration; Wires; Wiring;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2002.802260
  • Filename
    1043903