Analysis of Temperature Distribution in Stacked IC With On-Chip Sensing Device Arrays

Temperature distributions in 3-D integrated circuits (ICs) are analyzed with a test structure, which has a top-tier chip attached on a bottom dummy chip with adhesive layer. The devices with four kinds of top-tier chip thickness tSi of 50-410 μm were fabricated by a standard 0.18 μm CMOS process. The test structure consists of 24 sensor blocks, each of which has sensor p-n diodes, an on-chip heater resistor, and selector switches. The temperature distributions of the top-tier test chip under the constant and pulsed heater power were analyzed by both measurements and thermal simulations. Temperature T, which decreases with the distance L, is proportional to the reciprocal of L (1/L). Stacking effects on the temperature distributions become clear for the device with thinnertSi, and t_Si = 50 μm device has a different proportional constant for the region of larger L. Thermal simulations with an entire chip model show similar temperature distributions and the effects of bonding pads. Thermal transient phenomena in stacked ICs were analyzed under the pulsed heating and compared with simulation results. T rises abruptly after the heating pulse input and then gradually increases, and the thermal simulation reproduces the similar results. The test structure and the simulation modeling can provide an effective way for analysis of thermal conduction in stacked ICs.