• DocumentCode
    853591
  • Title

    An optimization study of underfill dispensing volume

  • Author

    Chia, YewChoon ; Yam, HongSee ; Lim, S.H. ; Chian, K.S. ; Yi, Sung ; Chen, William T.

  • Author_Institution
    Electron. Assembly Div., Seagate Technol. Inc., Singapore
  • Volume
    26
  • Issue
    3
  • fYear
    2003
  • fDate
    7/1/2003 12:00:00 AM
  • Firstpage
    205
  • Lastpage
    210
  • Abstract
    The underfill dispensing volume has been modeled and verified through both experiments and application of statistical technique. The model established is capable of estimating the operating range of the dispensing volume of a defined flip chip assembly and is targeted to reduce wastage as well whilst fulfilling the reliability requirement. The model has taken into consideration the reliability factor, e.g., presence of fillet; manufacturing tolerance of bumps size and standoff variation. In this study, the actual volume for flip chip assemblies prepared in a controlled manner, so that fillets were seen on all sides, was compared with the recommended underfill volume. It was found that the model tended to yield a higher volume and it is concluded that this variation is related to the over estimation of the fillet element in the formulation. For reliability assessment, these flip chip assemblies were examined under C-mode SAM and no voids were found. These flip chip assemblies also passed electrical testing after 500 cycles of air to air thermal cycles and therefore are proven to meet the reliability requirement.
  • Keywords
    circuit optimisation; electronics packaging; flip-chip devices; optimised production technology; soldering; tolerance analysis; C-mode SAM; air thermal cycles; bumps size; defined flip chip assembly; electrical testing; independent random variables; manufacturing tolerance; operating range; peripheral fillet; reliability factor; solder bump; standoff variation; underfill dispensing volume; underfill model; wastage reduction; Assembly systems; Circuit testing; Costs; Flip chip; Laboratories; Printed circuits; Production engineering; Silicon; Virtual manufacturing; Yield estimation;
  • fLanguage
    English
  • Journal_Title
    Electronics Packaging Manufacturing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1521-334X
  • Type

    jour

  • DOI
    10.1109/TEPM.2003.820812
  • Filename
    1256722