Title :
Chain: a delay-insensitive chip area interconnect
Author :
Bainbridge, John ; Furber, Steve
Author_Institution :
Dept. of Comput. Sci., Manchester Univ., UK
Abstract :
The increasing complexity of system-on-a-chip designs exposes the limits imposed by the standard synchronous bus. The authors propose a mixed system as a solution.
Keywords :
integrated circuit interconnections; system-on-chip; Chain; delay-insensitive chip area interconnect; mixed system; synchronous bus; system-on-a-chip designs; Asynchronous circuits; Clocks; Delay; Encoding; Integrated circuit interconnections; Latches; Network-on-a-chip; Pipelines; System-on-a-chip; Wire;
Journal_Title :
Micro, IEEE
DOI :
10.1109/MM.2002.1044296
