• DocumentCode
    853906
  • Title

    Chain: a delay-insensitive chip area interconnect

  • Author

    Bainbridge, John ; Furber, Steve

  • Author_Institution
    Dept. of Comput. Sci., Manchester Univ., UK
  • Volume
    22
  • Issue
    5
  • fYear
    2002
  • Firstpage
    16
  • Lastpage
    23
  • Abstract
    The increasing complexity of system-on-a-chip designs exposes the limits imposed by the standard synchronous bus. The authors propose a mixed system as a solution.
  • Keywords
    integrated circuit interconnections; system-on-chip; Chain; delay-insensitive chip area interconnect; mixed system; synchronous bus; system-on-a-chip designs; Asynchronous circuits; Clocks; Delay; Encoding; Integrated circuit interconnections; Latches; Network-on-a-chip; Pipelines; System-on-a-chip; Wire;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2002.1044296
  • Filename
    1044296
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=853906