Title :
Coping with latency in SOC design
Author :
Carloni, Luca P. ; Sangiovanni-Vincentelli, Alberto L.
Author_Institution :
California Univ., Berkeley, CA, USA
Abstract :
Latency-insensitive design is the foundation of a correct-by-construction methodology for SOC design. This approach can handle latency´s increasing impact on deep-submicron technologies and facilitate the reuse of intellectual-property cores for building complex systems on chips, reducing the number of costly iterations in the design process
Keywords :
application specific integrated circuits; integrated circuit technology; logic design; SOC design; correct-by-construction methodology; deep-submicron technologies; intellectual-property cores; latency-insensitive design; Assembly; Delay; Design methodology; Electronics industry; Microprocessors; Power system interconnection; Process design; Signal design; System-on-a-chip; Time to market;
Journal_Title :
Micro, IEEE
DOI :
10.1109/MM.2002.1044297
