Abstract :
The Eclipse network-on-a-chip architecture uses a sophisticated parallel programming model, realized through multithreaded processors, interleaved memory modules, and a high-capacity interconnection network to support system-on-a-chip designs
Keywords :
interleaved storage; multi-threading; parallel architectures; parallel machines; reconfigurable architectures; Eclipse network-on-a-chip architecture; embedded chip-level integrated parallel supercomputer; high-capacity interconnection network; interleaved memory modules; multithreaded processors; parallel programming model; system-on-a-chip designs; Computer architecture; Concurrent computing; Design methodology; Network-on-a-chip; Parallel processing; Parallel programming; Phase change random access memory; Synchronization; System-on-a-chip; Yarn;
