• DocumentCode
    853957
  • Title

    A hierarchical test methodology for systems on chip

  • Author

    Li, Jin-Fu ; Huang, Hsin-Jung ; Chen, Jeng-Bin ; Su, Chih-Pin ; Wu, Cheng-Wen ; Cheng, Chuang ; Chen, Shao-I ; Hwang, Chi-Yi ; Lin, Hsiao-Ping

  • Author_Institution
    Nat. Central Univ., Chung-li, Taiwan
  • Volume
    22
  • Issue
    5
  • fYear
    2002
  • Firstpage
    69
  • Lastpage
    81
  • Abstract
    We present a hierarchical test methodology for testing a SOC with heterogeneous cores, including the 1149.1-wrapped, P1500-wrapped, and BIST memory cores. We propose an 1149.1-based hierarchical test manager that also provides P1500 test control signals. This scheme includes a memory BIST interface, providing both serial and parallel access ports for BIST circuits. Our approach offers low area and pin overhead, and high flexibility
  • Keywords
    built-in self test; reconfigurable architectures; 1149.1-wrapped memory cores; BIST memory cores; P1500 test control signals; P1500 wrapped memory cores; heterogeneous cores; hierarchical test methodology; memory BIST interface; parallel access ports; serial access ports; Automatic control; Automatic testing; Automation; Built-in self-test; Circuit testing; Clocks; Registers; System testing; System-on-a-chip; Test pattern generators;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2002.1044301
  • Filename
    1044301
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=853957