50-gbit/s InP HEMT 4 : 1 multiplexer/1 : 4 demultiplexer chip set with a multiphase clock architecture

Author

Sano, Kimikazu ; Murata, Koichi ; Kitabayashi, Hiroto ; Sugitani, Suehiro ; Sugahara, Hirohiko ; Enoki, Takatomo

Author_Institution

NTT Photonics Labs., NTT Corp., Kanagawa, Japan

Volume

51

Issue

12

fYear

2003

Firstpage

2548

Lastpage

2554

Abstract

A 50-Gbit/s InP high electron-mobility transistor (HEMT) chip set of 4 : 1 multiplexer (MUX) and 1 : 4 demultiplexer (DMUX) integrated circuits (ICs) with a multiphase clock (MPC) architecture is described. The MPC architecture employs a quarter-rate four-phase clock generated by a toggle flip-flop inside the ICs, which reduces the number of circuit elements and lowers the power consumption. The fabricated 4 : 1 MUX and 1 : 4 DMUX ICs exhibited 50-Gbit/s error-free operations for 2³¹-1 pseudorandom bit sequences with 1.71- and 1.42-W power consumption, respectively. Compared to conventional tree-type 4 : 1 MUX and 1 : 4 DMUX ICs using InP HEMTs, the MPC 4 : 1 MUX and 1 : 4 DMUX ICs operate at the same operating speed with less than one-third power consumption.

Keywords

HEMT integrated circuits; III-V semiconductors; clocks; demultiplexing equipment; flip-flops; indium compounds; multiplexing equipment; power consumption; random sequences; 1.42 W; 1.71 W; 1:4 demultiplexer integrated circuits; 4:1 multiplexer/1:4 demultiplexer chip set; 50 Gbit/s; 50-Gbit/s error-free operation; InP; InP HEMT; conventional tree-type 4:1 MUX; high electron-mobility transistor; multiphase clock architecture; power consumption; pseudorandom bit sequence; quarter-rate four-phase clock; toggle flip-flop; Circuits; Clocks; Energy consumption; Error-free operation; Flip-flops; HEMTs; Indium phosphide; MODFETs; Multiplexing; Power generation;

fLanguage

English

Journal_Title

Microwave Theory and Techniques, IEEE Transactions on

Publisher

ieee

ISSN

0018-9480

Type

jour

DOI

10.1109/TMTT.2003.819205

Filename

1256788