Practical "building-in reliability" approaches for semiconductor manufacturing

To cope with the fast advancement of the semiconductor technology and customers´ expectations toward performance, service, delivery, quality and reliability, it is necessary to identify defect lots earlier in the production lines. This makes the conventional package-level reliability tests unsuitable for the modern semiconductor industries due to the long cycle time. The BIR (building-in reliability) methodology, on the contrary, preserves the merits of fast response, early alarm and closed-loop control. For semiconductor manufacturing, the BIR system has two major components: WLR (wafer-level reliability) and the BIR database, which enable us to make use of prior information to reduce risk and time to market. A thorough introduction on BIR system is given in this paper. The use of the BIR database, which is common in the aerospace development, resembles the Bayes approach in statistics. The proposed WLR system includes 4 fundamental elements: WLR design, WLR assessment, WLR baseline and WLR control. Practical concerns, implementations, and examples are depicted on these elements to clarify the WLR applications to the IC (integrated circuit) industries. In Section V, the example 2 on EM test indicates the procedures on formulating the control schemes. Recent studies on WLR and the BIR database after 1994 are also reviewed and described. Promising extensions on BIR and future work are presented. The widespread use of WLR implementations is crucial in solving complex reliability problems.