Latent effects due to ESD in CMOS integrated circuits: review and experiments

A review of the current information published on the subject of EOS/ESD latent failures is presented. In order to gain a better understanding of the phenomena involved in the input protection networks of CMOS integrated circuits, measurements were performed on both commercially available integrated circuits and a set of custom designed and fabricated devices. The tests investigated the effects of electrical stress, thermal shock, exposure to ultraviolet light, and thermal annealing. The results demonstrate the presence of latent failures in CMOS integrated circuits following exposure to ESD. The cumulative effect of repeated discharge can be partially alleviated using thermal annealing or exposure to light. A charge injection model is proposed to interpret the results