Title :
An efficient graph-based steiner tree heuristic for the global routing of macro cells
Author :
Gréwal, G. ; Xu, M.
Keywords :
Clocks; Integrated circuit interconnections; Rivers; Routing; Silicon compiler; Steiner trees; Testing; Very large scale integration; Wires;
Journal_Title :
Electrical and Computer Engineering, Canadian Journal of
DOI :
10.1109/CJECE.2006.259174
