An efficient graph-based steiner tree heuristic for the global routing of macro cells

Author

Gréwal, G. ; Xu, M.

Volume

Issue

fYear

2006

Firstpage

211

Lastpage

219

Keywords

Clocks; Integrated circuit interconnections; Rivers; Routing; Silicon compiler; Steiner trees; Testing; Very large scale integration; Wires;

fLanguage

English

Journal_Title

Electrical and Computer Engineering, Canadian Journal of

Publisher

ieee

ISSN

0840-8688

Type

DOI

10.1109/CJECE.2006.259174

Filename

4028913

Link To Document