DocumentCode
858622
Title
Optimal synthesis of algorithm-specific lower-dimensional processor arrays
Author
Ganapathy, Kumar N. ; Wah, Benjamin W.
Author_Institution
Telecommun. Div., Rockwell Int. Corp., Newport Beach, CA, USA
Volume
7
Issue
3
fYear
1996
fDate
3/1/1996 12:00:00 AM
Firstpage
274
Lastpage
287
Abstract
Processor arrays are frequently used to deliver high performance in many applications with computationally intensive operations. This paper presents the general parameter method (GPM), a systematic parameter-based approach for synthesizing such algorithm-specific architectures. GPM can synthesize processor arrays of any lower dimension from a uniform-recurrence description of the algorithm. The design objective is a general nonlinear and nonmonotonic user-specified function, and depends on attributes such as computation time of the recurrence on the processor array, completion time, load time, and drain time. In addition, bounds on some or all of these attributes can be specified. GPM performs an efficient search of polynomial complexity to find the optimal design satisfying the user-specified design constraints. As an illustration, we show how GPM can be used to find optimal linear processor arrays for computing transitive closures. We consider design objectives that minimize computation time, or processor count, or completion time (including load and drain times), and user-specified constraints on number of processing elements and/or computation/completion times. We show that GPM can be used to obtain optimal designs that trade between number of processing elements and completion time, thereby allowing the designer to choose a design that best meets the specified design objectives. We also show the equivalence between the model assumed in GPM and that in the popular dependence-based methods. Consequently, GPM can be used to find optimal designs for both models
Keywords
computational complexity; logic design; parallel processing; systolic arrays; algorithm-specific architectures; algorithm-specific lower-dimensional processor arrays; attributes; completion time; design objectives; drain time; equivalence; general parameter method; load time; optimal synthesis; polynomial complexity; transitive closures; uniform-recurrence description; Computer applications; Computer architecture; High performance computing; Polynomials; Process design; Systolic arrays; Time factors; Very large scale integration;
fLanguage
English
Journal_Title
Parallel and Distributed Systems, IEEE Transactions on
Publisher
ieee
ISSN
1045-9219
Type
jour
DOI
10.1109/71.491581
Filename
491581
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