VLSI architecture for high-speed rank and median filtering

Author

Arambepola, B.

Author_Institution

GEC-Marconi Res. Centre, Chelmsford

Volume

Issue

fYear

1988

fDate

9/1/1988 12:00:00 AM

Firstpage

1179

Lastpage

1180

Abstract

A VLSI architecture is presented for high-speed 1D and multidimensional rank filtering. The filter also provides the location of the output sample in the input data window. The rank, size and shape of the filter are variable

Keywords

VLSI; digital filters; digital integrated circuits; picture processing; 1D rank filtering; VLSI architecture; digital image filtering; high speed filtering; input data window; median filtering; multidimensional rank filtering;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

Filename

19619

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=858992