Performance Evaluation of Partial Response Targets for Perpendicular Recording Using Field Programmable Gate Arrays

We present the results of performance evaluation of partial response (PR) targets for perpendicular recording by simulation using a field programmable gate array (FPGA). Previous research proposed several PR targets for perpendicular recording channels. We evaluated the bit error rate (BER) performance of those PR targets. Different PR targets led to not only different BERs for given signal-to-noise ratios (SNRs), but also different slopes of BER versus SNR curves. The result can be explained in terms of error event distributions of the corresponding PR targets. In the FPGA simulation, additive white Gaussian noise was used, but no jitter noise was introduced. The soft output Viterbi algorithm is used as the channel detector. A rate-8/9 low-density parity check code with code length 4923 and column weight 3 is used as the error correcting code. Two channel iterations are applied. We attain BERs as low as 10^-12. Our results also show that the BER behavior of the PR4 target is significantly different from that of the [1 2 2 1] target