Title :
Adaptive supply serial links with sub-1-V operation and per-pin clock recovery
Author :
Kim, Jaeha ; Horowitz, Mark A.
Author_Institution :
Comput. Syst. Lab., Stanford Univ., CA, USA
fDate :
11/1/2002 12:00:00 AM
Abstract :
The application of adaptive power-supply regulation is extended to serial links. The adaptive supply maximizes the energy-efficiency of the I/O circuits and serves as a global bias to scale the link properties optimally with the bitrate. Parallelism in transceivers and the use of multiphase clocks increase the bitrate to a multiple of the clock frequency and, hence, enable the low frequency low-voltage operation to reduce power while meeting the specified bitrate. Two key designs to enable this power saving are presented: parallelized transceivers for low-voltage operation and dual-loop architecture phase/delay-locked loop for multiphase clock distribution. A prototype chip fabricated in 0.25-μm CMOS process operates at 0.65-5.0 Gb/s while dissipating 9.7-380 mW.
Keywords :
CMOS integrated circuits; adaptive control; circuit feedback; data communication; delay lock loops; digital control; low-power electronics; mixed analogue-digital integrated circuits; phase locked loops; power supply circuits; synchronisation; timing; transceivers; voltage regulators; 0.25 micron; 0.65 to 5 Gbit/s; 1 V; 9.7 to 380 mW; CMOS process; I/O circuits; LF LV operation; adaptive power-supply regulation; adaptive supply serial links; clock recovery DLL; clock recovery PLL; dual-loop architecture PLL/DLL; high-speed interfaces; low frequency operation; low-voltage operation; multiphase clock distribution; multiphase clocks; parallelized transceivers; power saving; specified bitrate; sub-1-V operation; Bit rate; Circuits; Clocks; Delay; Frequency; Parallel processing; Phase locked loops; Power dissipation; Transceivers; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2002.803937
