DocumentCode
859669
Title
Selectively breaking data dependences to improve the utilization of idle cycles in algorithm level re-computing data paths
Author
Wu, Kaijie ; Karri, Ramesh
Author_Institution
Dept. of Electr. & Comput. Eng., Polytech. Univ., Brooklyn, NY, USA
Volume
52
Issue
4
fYear
2003
Firstpage
501
Lastpage
511
Abstract
Although algorithm level re-computing techniques can trade-off the fault detection capability vs. time overhead of a Concurrent Error Detection (CED) scheme, they result in 100% time overhead when the strongest CED capability is achieved. Using the idle cycles in the data path to do the re-computation can reduce this time overhead. However, dependences between operations prevent the re-computation from fully utilizing the idle cycles. Deliberately breaking some of these data dependences can further reduce the time overhead associated with algorithm level re-computing. According to the experimental results the proposed technique, it brings time overhead down to 0-60% while the associated hardware overhead is from 12% to 50% depending on the design size.
Keywords
VLSI; circuit analysis computing; data analysis; error detection; fault tolerant computing; synchronisation; algorithm level re-computing technique; concurrent error detection scheme; data dependency; data path; deep submicron device; fault detection; hardware overhead; idle cycle utilization improvement; radiation hardening; time overhead; Combinational circuits; Data flow computing; Fault detection; Hardware; Logic design; Logic devices; Registers; Sequential circuits; Single event upset; Very large scale integration;
fLanguage
English
Journal_Title
Reliability, IEEE Transactions on
Publisher
ieee
ISSN
0018-9529
Type
jour
DOI
10.1109/TR.2003.821942
Filename
1260600
Link To Document