Title :
Implementation of a third-generation 1.1-GHz 64-bit microprocessor
Author :
Konstadinidis, Georgios K. ; Normoyle, Kevin ; Wong, Samson ; Bhutani, Sutikshan ; Stuimer, Harry ; Johnson, Timothy ; Smith, Alan ; Cheung, Daniel Y. ; Romano, Fabrizio ; Yu, Shifeng ; Oh, Sung-Hun ; Melamed, Victor ; Narayanan, Sridhar ; Bunsey, David ;
Author_Institution :
Sun Microsystems, Palo Alto, CA, USA
fDate :
11/1/2002 12:00:00 AM
Abstract :
This third-generation 1.1-GHz 64-bit UltraSPARC microprocessor provides 1-MB on-chip level-2 cache, 4-Gb/s off chip memory bandwidth, and a new 200 MHz JBus interface that supports one to four processors. The 87.5-million transistor chip is implemented in a seven-layer-metal copper 0.13-μm CMOS process and dissipates 53 W at 1.3 V and 1.1 GHz.
Keywords :
CMOS digital integrated circuits; VLSI; computer architecture; microprocessor chips; synchronisation; timing; very high speed integrated circuits; 0.13 micron; 1 MB; 1.1 GHz; 1.3 V; 200 MHz; 53 W; 64 bit; Cu; JBus interface; UltraSPARC microprocessor; high-speed IC; seven-layer-metal Cu CMOS; third-generation microprocessor; CMOS process; Central Processing Unit; Clocks; Copper; High speed integrated circuits; Microprocessors; Pipelines; Sun; System-on-a-chip; Workstations;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2002.803951
