Title :
A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller
Author :
Tanzawa, Toru ; Umezawa, Akira ; Taura, Tadayuki ; Shiga, Hitoshi ; Hara, Tokumasa ; Takano, Yoshinori ; Miyaba, Takeshi ; Tokiwa, Naoya ; Watanabe, Kentaro ; Watanabe, Hiroshi ; Masuda, Kazunori ; Naruke, Kiyomi ; Kato, Hideo ; Atsumi, Shigeru
Author_Institution :
Toshiba Corp., Yokohama, Japan
fDate :
11/1/2002 12:00:00 AM
Abstract :
The highest bit-density 64-Mb NOR flash memory with dual-operation function of 44 mm2 was developed by introducing negative-gate channel-erase NOR flash memory cell technology, 0.16-μm CMOS flash memory process technology, and four-bank hierarchical word-line and bit-line architecture. The chip has flexible block redundancy for high yield, a fast accurate word-line voltage controller for a fast erasing time of 0.5 s, and an eight-word page-read access capability for high read performance of an effective access time of 30 ns at a wide supply voltage range of 2.3-3.6 V.
Keywords :
CMOS memory circuits; NOR circuits; flash memories; integrated circuit reliability; memory architecture; redundancy; voltage regulators; 0.16 micron; 0.5 s; 2.3 to 3.6 V; 30 ns; 64 Mbit; CMOS flash memory process technology; NOR flash memory; dual-operation function; eight-word page-read access capability; fast word-line voltage controller; flexible block redundancy; four-bank hierarchical architecture; hierarchical bit-line architecture; hierarchical word-line architecture; negative-gate channel-erase memory cell technology; CMOS process; CMOS technology; Decoding; Flash memory; Flash memory cells; Microelectronics; Power supplies; Size control; Voltage control;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2002.802356
