Title :
Memory design using a one-transistor gain cell on SOI
Author :
Ohsawa, Takashi ; Fujita, Katsuyuki ; Higashi, Tomoki ; Iwata, Yoshihisa ; Kajiyama, Takeshi ; Asao, Yoshiyuki ; Sunouchi, Kazumasa
Author_Institution :
Memory Div., Toshiba Corp. Semicond. Co., Kanagawa, Japan
fDate :
11/1/2002 12:00:00 AM
Abstract :
A 512-kb memory has been developed featuring a one-transistor gain cell of size 7F2 (F = 0.18 μm) on SOI. The cell named the floating body transistor cell (FBC) has the ability to achieve a 4F2 cell using self-aligned contact technologies and is proved to be scalable with respect to a cell signal. A basic operation was verified by device simulation and hardware measurement. An array driving method is disclosed which makes selective write possible. A cell signal sensing system consisting of a pair of reference cells written opposite data and comparing the combined current with the doubled cell current is shown to be robust against cell parameter variations in process and temperature. A random access time of 40 ns was simulated. Nondestructive readout and Cb/Cs. free signal development drastically improve cell efficiency.
Keywords :
DRAM chips; integrated circuit design; nondestructive readout; silicon-on-insulator; 0.18 micron; 40 ns; 4F2 cell; 512 kbit; DRAM cell; SOI; Si; array driving method; cell signal sensing system; floating body transistor cell; memory design; nondestructive readout; one-transistor gain cell; reference cells; selective write; self-aligned contact technologies; Capacitors; Hardware; Large scale integration; MOSFET circuits; Random access memory; Research and development; Robustness; Signal processing; Silicon on insulator technology; Transistors;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2002.802359
