A 600-MHz VLIW DSP

Author

Agarwala, Sanjive ; Anderson, Timothy ; Hill, Anthony ; Ales, Michael D. ; Damodaran, Raguram ; Wiley, Paul ; Mullinnix, Steven ; Leach, Jerald ; Lell, Anthony ; Gill, Michael ; Rajagopal, Arjun ; Chachad, Abhijeet ; Agarwala, Manisha ; Apostol, John ; Kr

Author_Institution

Texas Instruments Inc., Dallas, TX, USA

Volume

37

Issue

11

fYear

2002

fDate

11/1/2002 12:00:00 AM

Firstpage

1532

Lastpage

1544

Abstract

A 600-MHz VLIW digital signal processor (DSP) delivers 4800 MIPS, 2400 (16 b) or 4800 (8 b) million multiply accumulates (MMACs) at 0.3 mW/MMAC (16 b). The chip has 64M transistors and dissipates 719 mW at 600 MHz and 1.2 V, and 200 mW at 300 MHz and 0.9 V. It has an eight-way VLIW DSP core, a two-level memory system, and an I/O bandwidth of 2.4 GB/s. The chip integrates a c64X DSP core with Viterbi and turbo decoders. Architectural and circuit design approaches to achieve high performance and low power using a semi-custom standard cell methodology, while maintaining backward compatibility, are described. The chip is implemented in a 0.13-μm CMOS process with six layers of copper interconnect.

Keywords

CMOS digital integrated circuits; VLSI; Viterbi decoding; cache storage; circuit CAD; digital signal processing chips; file organisation; high level synthesis; high-speed integrated circuits; integrated circuit design; low-power electronics; memory architecture; parallel architectures; pipeline processing; timing; turbo codes; 0.13 micron; 0.9 to 1.2 V; 16 bit; 2.4 GB/s; 200 to 718 mW; 300 to 600 MHz; 8 bit; CMOS process; Cu; Cu interconnect; DMA architecture; VLIW DSP core; VLIW digital signal processor; Viterbi decoders; architectural design approaches; backward compatibility; c64X DSP core; cache architecture; circuit design approaches; high performance; low power; semi-custom standard cell methodology; signal integrity; turbo decoders; two-level memory system; Bandwidth; CMOS process; Circuit synthesis; Copper; Decoding; Digital signal processing; Digital signal processing chips; Digital signal processors; VLIW; Viterbi algorithm;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.803954

Filename

1046099