Technique for compensation of errors in analogue multipliers

A new method for significantly reducing the effect of nonlinear errors on the performance of an analogue multiplier is presented. The method is especially well suited for switched-capacitor devices where time-shared (multiplexing) techniques can be easily employed. However, the method is quite general in nature and can be applied to any type of analogue integrated multiplier. The effectiveness of the technique has been checked through extensive simulation studies.