A Scalable Finite Field Multiplier

Author

Climent, J.J. ; Crespí, F. Garcia ; Grediaga, A.

Author_Institution

Catedratico de Univ. en la Univ. de Alicante, Alicante

Volume

6

Issue

7

fYear

2008

Firstpage

632

Lastpage

637

Abstract

The hardware - software codesign of cryptosistems, is the best solution to reach a reasonable yield in systems with resources limitation. In the last years, the cryptosistems based on elliptic curves (CEE) have acquired an increasing importance, managing at present to form a part of the industrial standards. In the underlying finite field of an CEE squaring and field multiplication is the next computational costly operations other than field inversion. This paper presents an algorithm for multiplication in binary fields GF(2^m) using a polynomial basis representation and with interleaving reduction. The finite field multiplier operates over a variety of binary fields and it is scalable.

Keywords

hardware-software codesign; polynomials; public key cryptography; cryptosistems; elliptic curves; hardware-software codesign; interleaving reduction; polynomial basis representation; scalable finite field multiplier; Computational efficiency; Elliptic curve cryptography; Elliptic curves; Field programmable gate arrays; Galois fields; Hardware design languages; Interleaved codes; Polynomials; Very high speed integrated circuits; Very large scale integration; FPGA; binary field; finite field arithmetic; interleaving reduction; polynomial representation; scalable multiplier;

fLanguage

English

Journal_Title

Latin America Transactions, IEEE (Revista IEEE America Latina)

Publisher

ieee

ISSN

1548-0992

Type

jour

DOI

10.1109/TLA.2008.4917435

Filename

4917435