DocumentCode :
860680
Title :
Drain voltage induced barrier increasing of quantum-wire transistors
Author :
Reitzenstein, S. ; Worschech, L. ; Hartmann, D. ; Forchel, A.
Author_Institution :
Technische Phys., Wurzburg Univ., Germany
Volume :
40
Issue :
1
fYear :
2004
Firstpage :
75
Lastpage :
77
Abstract :
In-plane quantum-wire transistors based on a modulation-doped GaAs/AlGaAs heterostructure are studied in the threshold regime. It is found that the threshold voltage VT of a quantum wire transistor depends on the applied bias voltage in a parabolic way. In particular, VT increases in the strong nonlinear transport regime with increasing bias voltage, which is in contrast to the drain voltage induced barrier lowering observed for submicron transistors. The increase of VT by a barrier increase along the channel with increasing bias voltage due to a self-depletion is explained.
Keywords :
III-V semiconductors; aluminium compounds; gallium arsenide; high electron mobility transistors; semiconductor quantum wires; two-dimensional electron gas; GaAs-AlGaAs; applied bias voltage; drain reservoir; drain voltage induced barrier increase; high quality two-dimensional electron gas; in-plane quantum-wire transistors; modulation-doped heterostructure; self-depletion; side-gated transistors; strong nonlinear transport regime; threshold regime;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:20040060
Filename :
1260687
Link To Document :
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