DocumentCode :
862081
Title :
An efficient JPEG2000 tier-1 coder hardware implementation for real-time video processing
Author :
Schumacher, Paul R.
Author_Institution :
Xilinx Res. Labs, Xilinx Inc., Longmont, CO, USA
Volume :
49
Issue :
4
fYear :
2003
Firstpage :
780
Lastpage :
786
Abstract :
The recently approved digital still image standard known as JPEG2000 promises to be an excellent image and video format for use with a large range of applications. For adoption of the standard to take place in the consumer marketplace, implementations supporting real time encoding and decoding of popular image and video formats must be created. It is a well-known fact that the major bottleneck of a JPEG2000 system is the bit/context modeling and arithmetic coding tasks. This paper discusses a hardware implementation of a tier-1 coder that exploits available parallelisms. The proposed technique described in this paper is approximately 50% faster than the best technique described in the literature.
Keywords :
decoding; field programmable gate arrays; real-time systems; video codecs; JPEG2000 tier-1 coder; arithmetic coding tasks; context modeling; digital still image standard; hardware implementation; real time decoding; real time encoding; real-time video processing; Arithmetic; Context modeling; Discrete wavelet transforms; Hardware; IEC standards; ISO standards; Image coding; Image processing; Military standards; Parallel processing;
fLanguage :
English
Journal_Title :
Consumer Electronics, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-3063
Type :
jour
DOI :
10.1109/TCE.2003.1261155
Filename :
1261155
Link To Document :
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