DocumentCode :
863420
Title :
Thread-parallel MPEG-2, MPEG-4 and H.264 video encoders for SoC multi-processor architectures
Author :
Jacobs, Tom R. ; Chouliaras, Vassilios A. ; Mulvaney, David J.
Author_Institution :
Loughborough Univ., UK
Volume :
52
Issue :
1
fYear :
2006
Firstpage :
269
Lastpage :
275
Abstract :
This study utilizes thread-level parallel techniques to significantly reduce the dynamic instruction count performance metric of the MPEG-2, MPEG-4 and H.264 video encoders. Such solutions are particularly applicable in portable devices as workload distribution among a number of parallel-executing processors decreases the individual processing requirements and allows for the real time video encoding. Due to the use of multiple processing engines in a consumer SoC the required clock frequency for real-time encoding, and hence power consumption, is likely to be considerably less than that of a single high-speed processor solution. The results presented demonstrate that reductions in dynamic instruction count in the range of 84% to 96% can be achieved for each of the encoders investigated.
Keywords :
microprocessor chips; multimedia systems; parallel architectures; system-on-chip; video coding; H.264 video encoders; MPEG-4; SoC multiprocessor architectures; real time video encoding; thread-level parallel techniques; thread-parallel MPEG-2; Bandwidth; Consumer products; Encoding; Energy consumption; Jacobian matrices; MPEG 4 Standard; Parallel processing; System-on-a-chip; Transform coding; Video compression;
fLanguage :
English
Journal_Title :
Consumer Electronics, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-3063
Type :
jour
DOI :
10.1109/TCE.2006.1605057
Filename :
1605057
Link To Document :
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