A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth

Author

Yan, Shouli ; Sánchez-Sinencio, Edgar

Author_Institution

Analog & Mixed-Signal Center, Texas A&M Univ., College Station, TX, USA

Volume

39

Issue

1

fYear

2004

Firstpage

75

Lastpage

86

Abstract

This paper presents the design and experimental results of a continuous-time ΣΔ modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time ΣΔ modulators is solved by our proposed architecture. A prototype third-order continuous-time ΣΔ modulator with 5-bit internal quantization was realized in a 0.5-μm double-poly triple-metal CMOS technology, with a chip area of 2.4 × 2.4 mm². Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz signal bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply.

Keywords

CMOS analogue integrated circuits; digital subscriber lines; digital-analogue conversion; jitter; modulators; pulse shaping circuits; quantisation (signal); sigma-delta modulation; 0.5 micron; 1.1 MHz; 3.3 V; 5 bit; 5-bit internal quantization; 62 mW; ADSL applications; MHz signal bandwidth; SNDR; SNR; clock jitter sensitivity reduction; continuous-time sigma-delta modulator; double-poly triple-metal CMOS technology; dynamic range; multibit nonreturn-to-zero DAC pulse shaping; nonzero excess loop delay; oversampling ratio; power dissipation; power supply; Bandwidth; CMOS technology; Clocks; Delay; Delta-sigma modulation; Dynamic range; Jitter; Optical signal processing; Prototypes; Pulse shaping methods;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.820856

Filename

1261290