Probability Level Dependence of Failure Mechanisms in Sub-20 nm NAND Flash Memory

Author

Duckseoung Kang ; Kyunghwan Lee ; Myounggon Kang ; Seongjun Seo ; Dong Hua Li ; Yuchul Hwang ; Hyungcheol Shin

Author_Institution

Inter-Univ. Semicond. Res. Center, Seoul Nat. Univ., Seoul, South Korea

Volume

35

Issue

3

fYear

2014

fDate

Mar-14

Firstpage

348

Lastpage

350

Abstract

We extracted final ΔV_th, time constant, and activation energy (E_a) of each mechanism in retention characteristics of sub-20-nm NAND flash main-chip according to the probability level (P level) of V_th cumulative probability distribution. As a result, we confirmed that at lower P level, the final ΔV_th of each mechanism increases sensitively according to P/E cycling stress. Temperature dependence of the final ΔV_th of each mechanism also increases with lowering P level, whereas trap-assisted tunneling (TAT) mechanism of corner area has complex characteristics on temperature. Interface trap recovery, TAT (plane), and TAT (corner) mechanism have larger E_a at high P level, whereas the E_a of detrapping mechanism decreases because of barrier lowering effect.

Keywords

NAND circuits; failure analysis; flash memories; interface states; probability; tunnelling; NAND flash main-chip; NAND flash memory; P-E cycling stress; TAT; activation energy; barrier lowering effect; cumulative probability distribution; detrapping mechanism; failure mechanisms; interface trap recovery; probability level dependence; retention characteristics; size 20 nm; time constant; trap assisted tunneling; Ash; Electron devices; Electron traps; Failure analysis; Flash memories; Temperature dependence; Temperature sensors; NAND flash memory; P level; activation energy $(E_{a})$ ; detrapping mechanism; failure mechanism; interface trap recovery; temperature dependence; trap-assisted tunneling (TAT);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2014.2301164

Filename

6730693