A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM

Author

Hamamoto, Takeshi ; Furutani, Kiyohiro ; Kubo, Takashi ; Kawasaki, Satoshi ; Iga, Hironori ; Kono, Takashi ; Konishi, Yasuhiro ; Yoshihara, Tsutomu

Author_Institution

Memory Design Dept., Renesas Technol. Corp., Hyogo, Japan

Volume

39

Issue

1

fYear

2004

Firstpage

194

Lastpage

206

Abstract

This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits are reduced by a hierarchical phase comparing architecture and a replica check method with slow tester. Further, an improved phase interpolating method suppresses jitters caused by a boundary of the fine and coarse delays. A 512-Mb test device is fabricated using a 0.13-μm DRAM process technology, in which skew and jitter suppressed 667-Mb/s (333-MHz) DDR operation has been verified.

Keywords

CMOS memory circuits; DRAM chips; delay lock loops; jitter; 0.13 micron; 333 MHz; 512 Mbit; 512-Mb DDR SDRAM; 512-Mb test device; 667 Mbit/s; CMOS process technology; DRAM process technology; all-digital delay-locked loop; clock input; coarse delays; data output circuits; digital DLL architecture; double-data-rate; fine delays; hierarchical phase comparing architecture; jitter suppression; phase interpolating method; replica adjusting techniques; replica check method; skew suppression; slow tester; Circuit testing; Clocks; DRAM chips; Delay lines; Frequency; High-speed electronics; Jitter; Random access memory; SDRAM; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.820851

Filename

1261301