Parametric macro-modeling of hot-carrier-induced dynamic degradation in MOS VLSI circuits

A macro-model approach is presented for the parametric evaluation of hot-carrier-related degradation of NMOS transistors operating in digital logic circuit environment. Simple design-for-reliability rules based on layout geometry are proposed for various NMOS/CMOS circuits, and for various operating conditions. It is shown that for a wide class of CMOS and NMOS logic gates, the performance degradation due to dynamic hot-carrier effects can be expressed as a function of the NMOS transistor channel width W_n, the load capacitance C_L, and the input voltage rise time. The parametric design-for-reliability rules devised in this work can also be used for geometry-based early diagnosis of potential reliability problems in CMOS circuits