Parametric macro-modeling of hot-carrier-induced dynamic degradation in MOS VLSI circuits

Author

Leblebici, Y. ; Sun, W. ; Kang, S.M.

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

Volume

40

Issue

3

fYear

1993

fDate

3/1/1993 12:00:00 AM

Firstpage

673

Lastpage

676

Abstract

A macro-model approach is presented for the parametric evaluation of hot-carrier-related degradation of NMOS transistors operating in digital logic circuit environment. Simple design-for-reliability rules based on layout geometry are proposed for various NMOS/CMOS circuits, and for various operating conditions. It is shown that for a wide class of CMOS and NMOS logic gates, the performance degradation due to dynamic hot-carrier effects can be expressed as a function of the NMOS transistor channel width W_n, the load capacitance C_L, and the input voltage rise time. The parametric design-for-reliability rules devised in this work can also be used for geometry-based early diagnosis of potential reliability problems in CMOS circuits

Keywords

CMOS integrated circuits; MOS integrated circuits; VLSI; circuit reliability; hot carriers; integrated logic circuits; semiconductor device models; CMOS circuits; MOS VLSI circuits; NMOS transistors; design-for-reliability rules; digital logic circuit environment; dynamic degradation; hot-carrier effects; input voltage rise time; layout geometry; load capacitance; transistor channel width; CMOS logic circuits; Capacitance; Degradation; Geometry; Hot carrier effects; Hot carriers; Logic circuits; Logic gates; MOS devices; MOSFETs;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.199342

Filename

199342