High-voltage amorphous silicon thin-film transistors

High-voltage MOSFETs have been fabricated in a large-area thin-film amorphous silicon technology. The transistors have an offset gate structure which allows them to operate at an excess of 400 V. Basic fabrication steps and structure are discussed. These transistors have a gate-controlled region in series with an offset region where the current is space charge limited. The I_D-V_D characteristics exhibit a unique instability under drain voltage stress; there is a parallel shift in the I_D versus V_D characteristic to a higher V_D. This instability arises from the creation of localized states in the a-Si during depletion. It is analyzed through experiment and two-dimensional simulation. Structural variations are described, including the application of a field plate, to stabilize transistor drive current. Reliability and process uniformity are discussed for arrays of transistors. An appropriate circuit simulation model is discussed. Operation of output drive circuits with high-voltage thin-film transistors (TFTs) is shown, and the application of these to an electrographic plotter is described