Efficient testing and diagnosis of faulty power switches in SOCs

The use of power switches in modern system chips (SOCs) is inevitable as they allow for efficient on-chip static power management. Leakage is one of the main hurdles in low-power applications. Power switches enable power gating functionality, that is one or more parts of the SOC can be powered-off during standby mode thus leading to savings in the SOC´s overall power consumption. To this end, a circuit and a method to test power switch is presented. The proposed method allows for the testing of on/off functionality. In case of segmented power switches, individual failing segments can be identified by using the proposed test strategy. The method only requires a small number of test patterns that are easy to generate. Furthermore, the proposed method is very scalable with the number of power switches and has a very small area-overhead