Transition time modeling in deep submicron CMOS

Author

Maurine, P. ; Rezzoug, M. ; Azemard, N. ; Auvergne, D.

Author_Institution

Lab. d´´Informatique, de Robotique et de Microelectronique de Montpellier, France

Volume

21

Issue

11

fYear

2002

fDate

11/1/2002 12:00:00 AM

Firstpage

1352

Lastpage

1363

Abstract

As generally recognized, the performance of a CMOS gate, such as propagation delay time or short circuit power dissipation, is strongly affected by the nonzero input signal transition time. This paper presents an analytical model of the transition time of CMOS structures. The authors first develop the model for inverters, considering fast and slow input signal conditions, over a large design range of input-output coupling capacitance and capacitive load. They then extend this model to more complex gates. The validity of the presented model is demonstrated through a comparison with HSPICE simulations on a 0.18 μm CMOS process.

Keywords

CMOS logic circuits; VLSI; delay estimation; integrated circuit modelling; logic gates; timing; 0.18 micron; CMOS gate; CMOS structures; analytical model; capacitive load; complex gates; deep submicron CMOS; input-output coupling capacitance; inverters; nonzero input signal transition time; propagation delay time; short circuit power dissipation; transition time modeling; Analytical models; Capacitance; Circuits; Delay effects; Delay estimation; Inverters; Power dissipation; Propagation delay; Semiconductor device modeling; Timing;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2002.804088

Filename

1047054