DocumentCode
864725
Title
Preferred direction Steiner trees
Author
Yildiz, Mehmet Can ; Madden, Patrick H.
Author_Institution
Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
Volume
21
Issue
11
fYear
2002
fDate
11/1/2002 12:00:00 AM
Firstpage
1368
Lastpage
1372
Abstract
The planar rectilinear Steiner tree problem has been extensively studied. The common formulation ignores circuit fabrication issues such as multiple routing layers, preferred routing directions, and vias between layers. In this paper, the authors extend a previously presented planar rectilinear Steiner tree heuristic to consider layer assignment, preferred routing direction restrictions, and via minimization. They use layer-specific routing costs, via costs, and have a minimum cost objective. Their approach combines the low computational complexity of modern geometry-based methods with much of the freedom enjoyed by graph-based methods. When routing costs mirror those of traditional planar rectilinear Steiner problems, the authors´ approach obtains close to 11% reductions in tree lengths, compared to minimum spanning trees; this is on par with the performance of the best available Steiner heuristics. When via costs are significant and layer costs differ, they observe average cost reductions of as much as 37%. Their method can also reduce the number of vias significantly.
Keywords
VLSI; circuit complexity; circuit layout CAD; integrated circuit layout; network routing; trees (mathematics); VLSI computer-aided design; geometric-based tree heuristic; graph-based methods; interconnect synthesis; layer assignment; layer-specific routing costs; low computational complexity; minimum cost objective; planar rectilinear Steiner tree; preferred direction Steiner trees; preferred routing direction restrictions; spanning tree problem; via costs; via minimization; Circuits; Computational complexity; Cost function; Fabrication; Minimization; Nonhomogeneous media; Routing; Steiner trees; Tree graphs; Very large scale integration;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2002.804105
Filename
1047056
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