Title :
X-masking during logic BIST and its impact on defect coverage
Author :
Tang, Yuyi ; Wunderlich, Hans-Joachim ; Engelke, Piet ; Polian, Ilia ; Becker, Bernd ; Schlöffel, Jürgen ; Hapke, Friedrich ; Wittke, Michael
Author_Institution :
Inst. of Comput. Archit. & Comput. Eng., Univ. of Stuttgart, Germany
Abstract :
We present a technique for making a circuit ready for logic built-in self test by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.
Keywords :
built-in self test; fault diagnosis; logic testing; X-masking; built-in self test; coverage loss; defect coverage; logic BIST; probabilistic model; resistive short defects; stuck-at n-detection based metric; Associate members; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Clocks; Costs; Logic circuits; Logic testing; Silicon; Defect coverage; X-masking; logic built-in self test (BIST); resistive bridging faults (RBFs);
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2005.863742
