A device model investigation of power Si/GaP heterojunction gate turn-off thyristors

Author

Kurata, Mamoru ; Azuma, Makoto

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

36

Issue

2

fYear

1989

fDate

2/1/1989 12:00:00 AM

Firstpage

424

Lastpage

432

Abstract

A device model investigation is made of power Si/GaP heterojunction gate-turn-off thyristors (GTOs), making use of previously published modeling tools, i.e. a one-dimensional model for GaAs/AlAs HBTs with a change in physical constants and a circuit simulator that allows the direct embedding of the one-dimensional model in an arbitrary circuit. By means of these modeling tools, design optimization is carried out for both homojunction and heterojunction GTOs. Comparison under the condition of an identical on-state voltage shows that the best heteroepitaxial GTO with an n-buffer layer exhibits an improvement in turn-off loss of a factor of 1.55 over the best homoepitaxial GTO of the same structure. This factor becomes 1.86 if a slight increase in the on-state voltage is permitted

Keywords

III-V semiconductors; elemental semiconductors; gallium arsenide; semiconductor device models; semiconductor junctions; silicon; thyristors; Si-GaP; design optimization; heteroepitaxial GTO; heterojunction GTOs; heterojunction gate turn-off thyristors; n-buffer layer; one-dimensional model; power GTO thyristors; semiconductors; turn-off loss; Cathodes; Circuit simulation; Gallium arsenide; Heterojunctions; Photonic band gap; Power system modeling; Predictive models; Silicon devices; Thyristors; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.19946

Filename

19946