• DocumentCode
    864764
  • Title

    Comments on "Carry checking/parity prediction adders and ALUs"

  • Author

    Rodríguez-Navarro, José J.

  • Author_Institution
    RWTH Aachen Univ., Germany
  • Volume
    14
  • Issue
    2
  • fYear
    2006
  • Firstpage
    212
  • Lastpage
    213
  • Abstract
    In this brief, it is shown that the checking or comparison of normal carries versus duplicated carries in a carry checking/parity prediction adder can be partially avoided, making it feasible to implement a less complex checker when using a robust logic style.
  • Keywords
    adders; ALU; carry checking; parity prediction adders; robust logic style; Boolean functions; Logic; Parity check codes; Prediction methods; Robustness; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2005.863739
  • Filename
    1605287
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=864764