Title :
A 2.5-D Memory-Logic Integration With Data-Pattern-Aware Memory Controller
Author :
Dongjun Xu ; Ningmei Yu ; Sai Manoj, P.D. ; Kanwen Wang ; Hao Yu ; Mingbin Yu
Author_Institution :
Xi´an Univ. of Technol., Xi´an, China
Abstract :
This paper presents silicon interposer-based 2.5-D integration of core and memory chips. Utilization of the channels through TSVs and interposer routing between the core and memory chips is maximized by bandwidth balancing enabled by space-time multiplexing of the channels with core clustering.
Keywords :
memory architecture; multiplexing; network routing; pattern clustering; 2.5D memory-logic integration; TSVs; core clustering; data-pattern-aware memory controller; interposer routing; memory chips; silicon interposer-based 2.5-D integration; Bandwidth allocation; Benchmark testing; Memory management; Microprocessors; Multiplexing; Quality of service; Three-dimensional displays; 2.5D integration; memory controller; memory-core integration; space-time multiplexing; through-silicon-interposer (TSI);
Journal_Title :
Design & Test, IEEE
DOI :
10.1109/MDAT.2015.2440413
